1. Field of the Invention
This disclosure relates to a test apparatus of an integrated circuit, and more particularly, to a parallel test apparatus and method of the integrated circuit capable of injecting a high test current.
2. Description of the Related Art
Generally, an integrated circuit device (hereinafter IC) is manufactured through multiple processes. Afterwards, a test process is performed to check whether the IC works properly and has any defects in its parts.
There are two types of test apparatus that can be used to perform the test process. One type is a single test apparatus that tests a single device under test (DUT) at one time and another type is a parallel test apparatus that tests several DUTs at the same time. The parallel test apparatus, which is very useful in mass production, is disclosed in U.S. patent application Ser. No. 6,480,978, entitled “Parallel Testing of Integrated Circuit Devices Using Cross-DUT and Within-DUT Comparisons” and Japanese Patent Publication No. 2001-176293, entitled “Test Method For Semiconductor Memory, And Test Device”.
FIG. 1 is a block diagram schematically illustrating a general apparatus to perform a parallel test on a plurality of devices under test (DUTs).
As illustrated in FIG. 1, four DUTs (DUT1˜DUT4) are connected to a test circuit unit 10. The DUT1 through DUT4 may each have two power pins (VDD, VDDQ), and the test circuit unit 10 may include a power supply providing a test current to the DUT1 through the DUT4, a memory set (not shown) storing a test data, and a compare unit (not shown) comparing data stored in the memory set and test devices from the DUT1 through the DUT4 and outputting whether the data is normal or abnormal.
The test circuit unit 10 includes a first through a third power source VS1, VS2, and VS3. The VDDs of DUT1 and DUT2 are connected to the first power source VS1, the VDDs of DUT3 and DUT 4 are connected to the second power source VS2, and the VDDQs of DUT1 through DUT4 are connected to the third power source VS3. Thus, DUT1 through DUT4 are connected to the test circuit 10 in a parallel manner.
In a parallel test apparatus having the above structure, if a predetermined voltage V is applied from the first through the third power source VS1, VS2, and VS3 in the test circuit unit 10, a test-performing current flows to the respective test devices of the DUT1 through the DUT4.
The VDDs of DUT1 and DUT2 are commonly connected to the first power source VS1, and thus the current of the first power source VS1 is distributed to each VDD of DUT1 and DUT2. For instance, if an 800 mA current is generated in the first power source VS1, a 400 mA current flows into each VDD of DUT1 and DUT2. This applies to the VDDs of DUT3 and DUT4, each having half of the current generated in the second power source VS2.
However, in a case where a high integrated memory device such as a double data rate RAM (DDR), a test current of 400 mA or more per unit test device is required. Thus, if a set of DUTs shares one power source, the test current provided is divided to each DUT. The amount of the test current divided depends on the number of DUTs. Therefore, it is difficult to provide the high test current to each DUT. In this case, test efficiency and product reliability is decreased because the test may be improperly performed in the devices requiring the high test current. In addition, production cost is increased since a new instrument including the strong power supply should be added to obtain the high test current.
Embodiments of the invention address these and other disadvantages of the conventional art.